Antenna effect in SOI process

 

之前沒想過，會再寫一篇跟antenna effect相關的文章。最近碰了SOI製程，才發現antenna effect在bulk和SOI製程裡有些不同，就簡單整理一下。

Fig. 1和Fig. 2分別是bulk和SOI製程下，NMOS的剖面圖。兩種製程最大的差別就是SOI多了那層BOX (buried oxide)，BOX會阻隔MOS和P-sub，原本source/drain到bulk或是n-well到p-sub的寄生diode將不再存在。所以原本bulk製程，我們只著重在閘極的antenna effect；而在SOI製程裡因缺少source/drain到bulk的寄生diode，閘極(Gate)、源極(Source)、汲極(Drain)的antenna effect將必須考慮。

在SOI製程裡，沒有共同的p-sub接地，所以antenna effect造成的damage將會是元件三點(G、D、S)裡，任兩點電壓差過大所造成的傷害。雖然製作過程中，每個點都可視為floating，電壓差過大的機率相對較小，但現在的nanosheet或GAA製程的gate oxide都超極薄的，還是很容易有damage。

在SOI製程裡解決antenna effect的方法還是跳線法以及加Antenna diode。跳線法可參考之前寫的文章-積體電路的天線效應 (Antenna Effect in IC)，來降低元件每個端點的電荷累積。至於加Antenna diode，首先要製程有提供diode，然後製程會要求在很低的金屬層(ex: Metal2)就要有網狀的GND mesh，來當共同放電的點(像bulk製程裡的p-sub)。

其實簡單來說，antenna eddect在SOI製程裡，有以下兩點。

1. 閘極(Gate)、源極(Source)、汲極(Drain)都要考慮antenna。
2. 使用antenna diode有更多的限制。

參考文獻 (Reference):
[1]M. Khare, et al., "Plasma Charging Damage Immunity in SOI Devices," in Proc. IEEE Int. Conf. on Solid State Devices and Material, pp. 222-223, 2000.

[2] T. Poiroux, et al., "Plasma Process-Induced Damage in SOC Devices," in Proc IEEE IEDM, pp. 97-100, 1999.

[3] T. B. Hook, "SOI Chip Design and Charging Damage," in proc. IEEE Int. Conf. on Integrated Circuit Design and Technology, 2008.

[4] M. Akbal, et al., "Plasma induced damage investigation in the fully depleted SOI technology," in proc. IEEE Int. Conf. on Integrated Circuit Design and Technology, pp. 119-122, 2014.

[5] M. Akbal, et al., "New insight in plasma charging impact on gate oxide breakdown in FDSOI technology," in proc. IEEE IRPS, pp.2.1-4, 2015

[6] Terence B. Hook and Mario M. Pelella, "SOI antennas and wafer bulk connection," in Proc. IEEE International SOI Conference, 2008.

延伸閱讀:

1. Introduction to LOD Effect (上) 
2. Introduction to LOD Effect (下)
3. Well Proximity Effect
4. OD Space Effect (OSE) 
5. Poly Space Effect (PSE)
6. Self-Heating Effect (SHE) 自我加熱效應
7. 積體電路的天線效應 (Antenna Effect in IC)