tag:blogger.com,1999:blog-9157671345275302973.comments2023-10-31T11:00:18.727+08:00BuBuChen的旅遊記事本BuBuChenhttp://www.blogger.com/profile/14583978202845639494noreply@blogger.comBlogger1132125tag:blogger.com,1999:blog-9157671345275302973.post-12542878949904749982023-10-31T11:00:18.727+08:002023-10-31T11:00:18.727+08:00謝謝分享,內容淺顯易懂深入淺出。謝謝分享,內容淺顯易懂深入淺出。Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-15320931440793184792023-09-14T19:36:03.259+08:002023-09-14T19:36:03.259+08:00有"measure eye"有"measure eye"BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-46641400730262856022023-09-13T10:39:46.448+08:002023-09-13T10:39:46.448+08:00请问可以测量眼高眼宽和其他相关项嘛?请问可以测量眼高眼宽和其他相关项嘛?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-57197099765090187422023-08-03T12:50:46.261+08:002023-08-03T12:50:46.261+08:00對,dram controller要決定。對,dram controller要決定。BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-24508089296759287102023-07-28T13:27:18.623+08:002023-07-28T13:27:18.623+08:00感謝學長無私分享!感謝學長無私分享!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-50832474981206325182023-06-02T08:52:32.371+08:002023-06-02T08:52:32.371+08:00一般來說,不論多複雜的low-to-high levelshifter 都是NMOS input、上...一般來說,不論多複雜的low-to-high levelshifter 都是NMOS input、上面是PMOS cross-couple,所以在input NMOS下拉路徑比cross-couplle的上拉路徑弱時,levelshifter的output就會翻不過去。而SNFP 且低溫的狀況,就是電路最差條件。BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-42003439713220294472023-06-01T17:15:59.291+08:002023-06-01T17:15:59.291+08:00Slow NMOS, Fast PMOS低溫下這個corner,請問為什麼這樣最worse? 是因為...Slow NMOS, Fast PMOS低溫下這個corner,請問為什麼這樣最worse? 是因為high to low?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-27030012312336461042023-03-30T10:59:55.212+08:002023-03-30T10:59:55.212+08:00GOOD +1GOOD +1Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-54928785901451601682023-02-15T08:55:42.002+08:002023-02-15T08:55:42.002+08:00這也是我第一個自己找到的寶~~~XD這也是我第一個自己找到的寶~~~XD水色漂泊https://www.blogger.com/profile/00991135365965957926noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-69668040869307337192023-02-08T23:17:37.286+08:002023-02-08T23:17:37.286+08:00DNW如果全區NMOS都包,多出來的面積我覺得不多。感覺是個很好跟substrate做隔離的東西。DNW如果全區NMOS都包,多出來的面積我覺得不多。感覺是個很好跟substrate做隔離的東西。公車奇想男https://www.blogger.com/profile/11399760019021543854noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-7301057114268014412023-01-10T16:11:28.276+08:002023-01-10T16:11:28.276+08:00了解!所以SoC會自己判斷需不需要使用Mask Write的樣子!了解!所以SoC會自己判斷需不需要使用Mask Write的樣子!Tedhttps://www.blogger.com/profile/11683305954117546701noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-39053740344686692542022-04-23T12:21:24.427+08:002022-04-23T12:21:24.427+08:00you are welcome.you are welcome.BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-52629970900277710992022-04-20T10:22:24.993+08:002022-04-20T10:22:24.993+08:00謝謝版主分享
謝謝版主分享<br />Jason Suhttps://www.blogger.com/profile/14098907071908144026noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-65182846732471876732022-03-23T21:36:33.988+08:002022-03-23T21:36:33.988+08:00感謝版主回覆^^文章都很優質~~感謝版主回覆^^文章都很優質~~Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-73468718458769028692022-03-22T00:13:20.337+08:002022-03-22T00:13:20.337+08:001. 右邊M1在製作時也會產生電荷,只是用跳線法時跟MN1無關,所以Fig.2沒畫出來
2. 電路上...1. 右邊M1在製作時也會產生電荷,只是用跳線法時跟MN1無關,所以Fig.2沒畫出來<br />2. 電路上任一點加上額外的元件(MOS、DIODE.....)都會增加負載BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-40012412282726700522022-03-21T22:50:30.287+08:002022-03-21T22:50:30.287+08:00想請教兩個問題
1. fig2 右邊的M1為什麼不會累積電荷?
2. diode太多增加loadin...想請教兩個問題<br />1. fig2 右邊的M1為什麼不會累積電荷?<br />2. diode太多增加loading的意思是什麼?<br />感謝Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-50054867004535159782022-03-08T09:20:23.388+08:002022-03-08T09:20:23.388+08:00我沒聽shared OD來降低noise的說法。XD
如果硬要這麼說,我猜是shared OD後, ...我沒聽shared OD來降低noise的說法。XD<br />如果硬要這麼說,我猜是shared OD後, S/D和substrate接觸面積變小,所以"比較"不易受substrate noise影響。BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-70014105216584554102022-03-06T23:30:54.920+08:002022-03-06T23:30:54.920+08:00OD如果都共用的話 除了縮小面積外
之前也有朋友說 可以降低noise
但一直沒有找到相關pape...OD如果都共用的話 除了縮小面積外<br />之前也有朋友說 可以降低noise <br />但一直沒有找到相關paper 不知道大哥有聽說過嗎?公車奇想男https://www.blogger.com/profile/11399760019021543854noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-27503514997659762692022-01-27T23:22:37.085+08:002022-01-27T23:22:37.085+08:00Hi Ted,
通常DQ是一次連續送八筆data,但有時並不是八筆都想要寫進DRAM裡,所以用DM...Hi Ted,<br /><br />通常DQ是一次連續送八筆data,但有時並不是八筆都想要寫進DRAM裡,所以用DM這個訊號把要寫進DRAM和不寫進DRAM的data標示出來。<br /><br />查了一下JEDEC standard,DDR4的DM是低電位時,其相對應的DQ是不要寫入DRAM的。BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-50144844624412527692022-01-25T15:07:19.499+08:002022-01-25T15:07:19.499+08:00您好,想請問DDR4的情況下,何謂DQ被DM框住阿?是指高電位還是低電位呢?DM的功用何在😯您好,想請問DDR4的情況下,何謂DQ被DM框住阿?是指高電位還是低電位呢?DM的功用何在😯Tedhttps://www.blogger.com/profile/11683305954117546701noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-60199646518963450242021-11-12T22:11:25.221+08:002021-11-12T22:11:25.221+08:00RDL也要喔。它也是在晶圓製程裡。RDL也要喔。它也是在晶圓製程裡。BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-9089526134227836202021-11-08T11:40:19.173+08:002021-11-08T11:40:19.173+08:00请问下WLCSP 的情况下,RDL 是否需要考虑天线效应呢?
感谢!请问下WLCSP 的情况下,RDL 是否需要考虑天线效应呢?<br />感谢!Anonymoushttps://www.blogger.com/profile/10563046298855841724noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-36434985839501161692021-10-13T23:31:29.266+08:002021-10-13T23:31:29.266+08:00結果是複雜的low-speed io without ESD結果是複雜的low-speed io without ESDAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-87763845439124959572021-03-05T15:42:27.373+08:002021-03-05T15:42:27.373+08:00感謝~~~感謝~~~BuBuChenhttps://www.blogger.com/profile/14583978202845639494noreply@blogger.comtag:blogger.com,1999:blog-9157671345275302973.post-18091569409793267262021-03-03T22:46:52.832+08:002021-03-03T22:46:52.832+08:00大大您的寫得太好了!大大您的寫得太好了!Anonymousnoreply@blogger.com