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2016年7月26日 星期二

Shih-Lun Chen's Publication List

新中華民國專利通過,來更新一下吧。

到今天2016/7/26為止,共發表了IEEE Regular Journal 4篇IEEE Brief Journal 3篇International Conference Paper 12篇;申請通過了美國專利7篇台灣專利8篇中國專利1篇

期刊、會議、專利篇數
Regular Journal (4)IEEE JSSC2
IEEE T-CAS11
IEEE T-VLSI1
Brief Journal (3)IEEE T-CAS23
International Conference Paper (12)IEEE ISSCC1
IEEE ASSCC1
IEEE ISCAS4
IEEE AP-ASIC3
IEEE ICECS1
IEEE APCCAS1
VLSI-DAT1
Patent (16)US Patent7
Taiwan Patent8
China Patent1


PUBLICATION LIST

(A) Regular Journal Papers (4)
[1] H.-Y. Huang and Shih-Lun Chen, “Interconnect accelerating techniques for sub-100 nm giga-scale systems,” IEEE Trans. VLSI Systems, vol.12, pp. 1192-1200, Nov. 2004.
[2] M.-D. Ker, Shih-Lun Chen, and C.-S. Tsai, “Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage process,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1100-1107, May 2006.
[3] M.-D. Ker, Shih-Lun Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. Circuits Syst. I: Regular Papers, vol.53, no.9, pp. 1934-1945, Sep. 2006.
[4] M.-D. Ker and Shih-Lun Chen, “Design of mixed-voltage I/O buffer by using NMOS-blocking technique,” IEEE J. Solid-State Circuits, vol. 41, no.10, pp. 2324-2333, Oct. 2006.

(B) Brief Journal Papers (3)
[1] Shih-Lun Chen and M.-D. Ker, “A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 52, no. 7, pp. 361-365, July 2005.
[2] Shih-Lun Chen and M.-D. Ker, “An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process,” IEEE Trans. Circuits Syst. II: Express Briefs, vol.54, no. 1, pp. 14-18, Jan. 2007.
[3] M.-D. Ker and Shih-Lun Chen, “Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes,” IEEE Trans. Circuits Syst. II: Express Briefs, vol.54, no. 1, pp. 47-51, Jan. 2007.

(C) International Conference Papers (12) 
[1] H.-Y. Huang and Shih-Lun Chen, “Input isolated sense amplifiers,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Scottsdale, Arizona, USA, May 2002, vol. 4, pp. 587-590.
[2] H.-Y. Huang and Shih-Lun Chen, “Self-isolated gain-enhanced sense amplifier,” in Proc. IEEE Asia-Pacific Conf. ASIC (AP-ASIC), Taipei, Taiwan, Aug. 2002, pp, 57-60.
[3] H.-Y. Huang and Shih-Lun Chen, “High-speed receivers for on-chip interconnections in deep-submicron process,” in Proc. IEEE Int. Conf. Electronics, Circuits, Syst. (ICECS), Sept. 2002, vol. 2, pp. 769-772.
[4] H.-Y. Huang and Shih-Lun Chen, “Threshold triggers and accelerator for deep submicron interconnection,” in Proc. IEEE Asia-Pacific Conf. Circuits Syst. (APCCAS), Oct. 2002, vol. 2, pp. 143-146.
[5] M.-D. Ker, Shih-Lun Chen, and C.-S. Tsai, “A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage process,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Vancouver, British Columbia, Canada, May 2004, vol. 1, pp. 321-325.
[6] Shih-Lun Chen and M.-D. Ker, “A new Schmitt trigger circuit in a 0.13 μm 1/2.5 V CMOS process to receive 3.3 V input signals,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Vancouver, British Columbia, Canada, May 2004, vol. 2, pp. 573-576.
[7] Shih-Lun Chen and M.-D. Ker, “A new output buffer for 3.3-V PCI-X applications in a 0.13 μm 1/2.5 V CMOS process,” in Proc. IEEE Asia-Pacific conf. ASIC (AP-ASIC), Fukuoka, Japan. Aug. 2004, pp. 112-115.
[8] H.-Y. Huang, C.-C. Wu, and Shih-Lun Chen, “Simultaneous current-mode bi-directional signaling for on-chip interconnection,” in Proc. IEEE Asia-Pacific conf. ASIC (AP-ASIC), Fukuoka, Japan, 2004, pp. 380-383.
[9] M.-D. Ker and Shih-Lun Chen, “Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD power supply,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 524-525, 614.
[10] M.-D. Ker, Shih-Lun Chen, and C.-S. Tsai, “Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Kobe, Japan, May 2005, pp. 1859-1862.
[11] M.-D. Ker and Shih-Lun Chen, “On-chip high-voltage charge pump circuit in standard CMOS process with polysilicon diodes,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Hsinchu, Taiwan, Nov. 2005, pp.157-160.
[12] Shih-Lun Chen, M.-J. Ho, Y.-M. Sun, M. W. Lin, and J.-C. Lai, “An all-digital delay-locked loop for high-speed memory interface applications,” in Proc. Int. Symp. VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 2014, pp.147-150.

(D) Other Conference Papers (4)
[1] H.-Y. Huang and Shih-Lun Chen, “Sense amplifiers for high-speed interconnection design,” in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Taiwan, Aug. 2001.
[2] H.-Y. Huang and Shih-Lun Chen, “Deep submicron interconnection triggers and accelerator,” in Proc. 13th VLSI Design/CAD Symp., Taitung, Taiwan, Aug. 2002.
[3] Shih-Lun Chen and M.-D. Ker, “Schmitt trigger circuit realized by only thin-gate-oxide devices to receive high-voltage input signals in a 0.13-μm CMOS process,” in Proc. 15th VLSI Design/CAD Symp., Kenting, Taiwan, Aug. 2004.
[4] H.-Y. Huang, C.-C. Wu, and Shih-Lun Chen, “Simultaneous current-mode bi-directional transceiver,” in Proc. 15th VLSI Design/CAD Symp., Kenting, Taiwan, Aug. 2004.

(E) U.S. Patents (7)
[1] H.-Y. Huang and Shih-Lun Chen, “Apparatus for capacitor-coupling acceleration,” U.S. Patent 6850089, Feb. 1, 2005.
[2] Shih-Lun Chen and M.-D. Ker, “Output buffer with low-voltage devices to drive high-voltage signals for PCI-X applications,” U.S. Patent 7046036, May 16, 2006.
[3] M.-D. Ker and Shih-Lun Chen, “Mixed-voltage I/O buffer with low-voltage devices,” U.S. Patent 7532034, May 12, 2009.
[4] M.-J. Ho and Shih-Lun Chen, “Delay lock loop (DLL) circuit for improving jitter,” U.S. Patent 8373479, Feb. 12, 2013.
[5] Shih-Lun Chen and M.-J. Ho, “Apparatus for reducing simultaneous switching noise,” U.S. Patent 8519752, Aug. 27, 2013.
[6] Shih-Lun Chen and M.-J. Ho, “Signal delay circuit and signal delay method,” U.S. Patent 8799821, July 15, 2014.
[7] M.-J. Ho, Shih-Lun Chen, and Y.-M. Sun “Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device,” U.S. Patent 9058898, June 16, 2015.

(F) R.O.C. (Taiwan) Patents (8)
[1] 陳世倫、柯明道, “利用低電壓元件組成的高電壓共容輸出緩衝器,” 中華民國發明專利,” April 1, 2005. (專利證書號 # I230507)。
[2] 陳世倫、柯明道, “可容忍高電壓輸入且用低電壓元件組成的史密特觸發器,” 中華民國發明專利,” April 1, 2005. (專利證書號 # I230510)。
[3] 黃弘一、陳世倫, “電容耦合裝置”中華民國發明專利,” June 11, 2006. (專利證書號 # I256771)
[4] 柯明道、陳世倫, “具有低電壓元件設計之混合電壓輸入/輸出緩衝器,” 中華民國發明專利,” Oct. 11, 2008. (專利證書號 # I302025)
[5] 何明瑾、陳世倫, “延遲鎖定迴路,” 中華民國發明專利,” Apr. 1, 2014. (專利證書號 # I433467)
[6] 陳世倫、何明瑾, “降低同步切換雜訊之電子裝置,” 中華民國發明專利,” June 1, 2014. (專利證書號 # I440306)
[7] 陳世倫、何明瑾, “訊號延遲電路和訊號延遲方法,” 中華民國發明專利,” Oct. 11, 2014. (專利證書號 # I456900)
[8] 何明瑾、陳世倫、孫郁明, “一種用以減少從一記憶體裝置讀取資料之延遲時間的記憶體介面電路,” 中華民國發明專利,” July 21, 2016. (專利證書號 # I543190)

(G) China Patents (1)
[7] 陳世倫、何明瑾, “信號延遲電路和信號延遲方法,” 中國發明專利,” Sep. 30, 2015 (專利公告號 #103124169)

2 則留言:

  1. 看了你的publication list,做了不少project, 很厉害啊。有点疑问,为什么这么多篇论文都是以导师作为第一作者呢? 这是你们学校的惯例吗?

    版主回覆:(01/13/2013 11:30:24 AM)


    是慣例啊~~XD

    回覆刪除